MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 271

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

37-sci_d
MOTOROLA
NOTE:
R8 — Received Bit 8
T8 — Transmitted Bit 8
DMARE — DMA Receive Enable Bit
To enable the SCRF bit to generate DMA service requests, the SCI
receive interrupt enable bit (SCRIE) must be set.
DMATE — DMA Transfer Enable Bit
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
This read/write bit enables the DMA to service SCI receiver DMA
service requests generated by the SCRF bit. Setting the DMARE bit
disables SCI receiver CPU interrupt requests. Reset clears the
DMARE bit.
This read/write bit enables SCI transmitter empty (SCTE) DMA
service requests. (See
the DMATE bit disables SCTE CPU interrupt requests. Reset clears
DMATE.
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1 = DMA enabled to service SCI receiver DMA service requests
0 = DMA not enabled to service SCI receiver DMA service requests
1 = SCTE DMA service requests enabled
0 = SCTE DMA service requests disabled
generated by the SCRF bit (SCI receiver CPU interrupt
requests disabled)
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
SCTE CPU interrupt requests disabled
SCTE CPU interrupt requests enabled
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SCI
SCI Status Register 1
on page 273.) Setting
MC68HC708XL36
I/O Registers
SCI
271