MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 183

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Interrupts
13-tim4_b
MOTOROLA
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels. MS0B
takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered
PWM operation. The TIM channel 2 registers (TCH2H:TCH2L) initially
control the PWM output. TIM status control register 2 (TSCR2) controls
and monitors the PWM signal from the linked channels. MS2B takes
priority over MS2A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. See
Status and Control Registers
The following TIM sources can generate interrupt requests:
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TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value rolls over to $0000 after matching the value in the
TIM counter modulo registers. The TIM overflow interrupt enable
bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
TIM channel flags (CH3F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests and TIM DMA service requests are
controlled by the channel x interrupt enable bit, CHxIE, and the
channel x DMA select bit, DMAxS. Channel x TIM CPU interrupt
requests are enabled when CHxIE:DMAxS = 1:0. Channel x
TIM DMA service requests are enabled when CHxIE:DMAxS =
1:1. CHxF and CHxIE are in the TIM channel x status and control
register. DMAxS is in the TIM DMA select register.
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TIM
on page 192.
TIM Channel
MC68HC708XL36
Interrupts
TIM
183