EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 126

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
UART Modem Control Register
This register is used to control and check the modem status, as listed in
Table 63. UART Modem Control Registers(UART0_MCTL = 00C4h, UART1_MCTL =
00D4h)
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:6]
5
MDM
4
LOOP
3
OUT2
2
OUT1
1
RTS
0
DTR
Value
0
1
0
1
0–1
0–1
0–1
0–1
00b
Description
Reserved—must be 00b.
MULTIDROP mode disabled.
MULTIDROP mode enabled. See
parity select definitions.
LOOP BACK mode is not enabled.
LOOP BACK mode is enabled.
The UART operates in internal LOOP BACK mode. The
transmit data output port is disconnected from the internal
transmit data output and set to 1. The receive data input port is
disconnected and internal receive data is connected to internal
transmit data. The modem status input ports are disconnected
and the four bits of the modem control register are connected
as modem status inputs. The two modem control output ports
(OUT1&2) are set to their inactive state.
No function in normal operation.
In LOOP BACK mode, this bit is connected to the DCD bit in
the UART Status Register.
No function in normal operation.
In LOOP BACK mode, this bit is connected to the RI bit in the
UART Status Register.
Request To Send
In normal operation, the RTS output port is the inverse of this
bit. In LOOP BACK mode, this bit is connected to the CTS bit in
the UART Status Register.
Data Terminal Ready
In normal operation, the DTR output port is the inverse of this
bit. In LOOP BACK mode, this bit is connected to the DSR bit
in the UART Status Register.
R
7
0
R
6
0
R/W
5
0
Universal Asynchronous Receiver/Transmitter
R/W
4
0
R/W
3
0
Table 62
Product Specification
R/W
2
0
eZ80F92/eZ80F93
on page 118 for
Table
R/W
1
0
63.
R/W
0
0
119