EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 134

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Receiver Frequency Divider
Table 67. IrDA Physical Layer 1.4 Pulse Durations Specifications (Continued)
The IrDA receiver uses a 6-bit frequency divider. The value is derived from the system
clock to measure IR_RxD pulses. The IrDA endec detects pulses that are within the IrDA
Physical Layer specified minimum and maximum ranges, with system clock frequencies
from 5 MHz up to 50 MHz.
The upper four bits of the frequency divider factor are set via the FREQ_DIV bit in the
IR_CTL register, based on the following equation:
The remaining lower two bits of the divider are set to
sponds to a period of 1.2 seconds. The FREQ_DIV value must be rounded to the nearest
integer and the resulting period of the 6-bit frequency divider must not be larger than
1.4 seconds, which is the IrDA defined minimum pulse width. If the period is greater than
1.4 seconds, FREQ_DIV should be rounded to the next lower integer. The receiver fre-
quency divider value versus the system clock frequency is shown in table, below.
Table 68. Frequency Divider Values
Frequency Divider Factor =
System Clock
< 5.0 MHz
5.0–7.8 MHz
7.8–10.8 MHz
10.8–13.6 MHz
13.6–25 MHz
25–50 MHz
Note: *The frequency divider is disabled when set to 00h.
Baud Rate
115200
57600
FREQ_DIV
00h*
01h
02h
03h
FLOOR[4-bit Frequency Divider Factor]
ROUND[4-bit Frequency Divider Factor]
Minimum Pulse
Width
1.41 s
1.41 s
System Clock Frequency (MHz)
Target Frequency of 3.33 MHz
Maximum Pulse
Width
4.34 s
2.23 s
03h
. The target frequency corre-
Product Specification
Infrared Encoder/Decoder
127