EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 32

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

Register Map
Table 3. Register Map
PS015313-0508
Address
(hex)
Programmable Reload Counter/Timers
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
Mnemonic
TMR0_CTL
TMR0_DR_L
TMR0_RR_L
TMR0_DR_H
TMR0_RR_H
TMR1_CTL
TMR1_DR_L
TMR1_RR_L
TMR1_DR_H
TMR1_RR_H
TMR2_CTL
TMR2_DR_L
TMR2_RR_L
TMR2_DR_H
TMR2_RR_H
TMR3_CTL
All on-chip peripheral registers are accessed in the I/O address space. All I/O operations
employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all
I/O operations (ADDR[23:16] =
range
not generated if the address space programmed for the I/O Chip Selects overlaps the
0080h
Registers at unused addresses within the
erals are not implemented. Read access to such addresses returns unpredictable values and
Write access produces no effect.
0080h
–
00FFh
–
00FFh
address range.
Name
Timer 0 Control Register
Timer 0 Data Register—Low Byte
Timer 0 Reload Register—Low Byte
Timer 0 Data Register—High Byte
Timer 0 Reload Register—High Byte
Timer 1 Control Register
Timer 1 Data Register—Low Byte
Timer 1 Reload Register—Low Byte
Timer 1 Data Register—High Byte
Timer 1 Reload Register—High Byte
Timer 2 Control Register
Timer 2 Data Register—Low Byte
Timer 2 Reload Register—Low Byte
Timer 2 Data Register—High Byte
Timer 2 Reload Register—High Byte
Timer 3 Control Register
are routed to the on-chip peripherals. External I/O Chip Selects are
UU
Table 3
). All I/O operations using 16-bit addresses within the
0080h
lists the register map for the eZ80F92 device.
–
00FFh
range assigned to on-chip periph-
Reset
(hex)
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Product Specification
00
eZ80F92/eZ80F93
Access
CPU
R/W
R/W
R/W
R/W
W
W
W
W
W
W
R
R
R
R
R
R
Register Map
Page
No
82
83
84
84
85
82
83
84
84
85
82
83
84
84
85
82
25