EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 164

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Table 87. I
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
7
IEN
6
ENAB
5
STA
4
STP
3
IFLG
2
AAK
[1:0]
2
C Control Registers(I2C_CTL = 00CBh)
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
00
R/W
I
I
The I
The I
Master mode START condition is sent.
Master mode start-transmit START condition on the bus.
Master mode STOP condition is sent.
Master mode stop-transmit STOP condition on the bus.
I
I
Not Acknowledge.
Acknowledge.
Reserved.
7
0
2
2
2
2
C interrupt is disabled.
C interrupt is enabled.
C interrupt flag is not set.
C interrupt flag is set.
2
2
C bus (SCL/SDA) is disabled and all inputs are ignored.
C bus (SCL/SDA) is enabled.
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
I2C Serial I/O Interface
R
1
0
R
0
0
157