EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 76

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

Table 24. Chip Select x Control Register(CS0_CTL = 00AAh, CS1_CTL = 00ADh, CS2_CTL =
PS015313-0508
Chip Select x Control Register
The Chip Select x Control register, listed in
the type of Chip Select, and sets the number of WAIT states. The reset state for the Chip
Select 0 Control register is
registers is
00B0h, CS3_CTL = 00B3h)
Bit
CS0_CTL Reset
CS1_CTL Reset
CS2_CTL Reset
CS3_CTL Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
[7:5]
CSx_WAIT
4
CSX_IO
3
CSx_EN
[2:0]
00h
.
Value Description
000
001
010
011
100
101
110
111
0
1
0
1
000
R/W
0 WAIT states are asserted when this Chip Select is active.
1 WAIT state is asserted when this Chip Select is active.
2 WAIT states are asserted when this Chip Select is active.
3 WAIT states are asserted when this Chip Select is active.
4 WAIT states are asserted when this Chip Select is active.
5 WAIT states are asserted when this Chip Select is active.
6 WAIT states are asserted when this Chip Select is active.
7 WAIT states are asserted when this Chip Select is active.
Chip Select is configured as a Memory Chip Select.
Chip Select is configured as an I/O Chip Select.
Chip Select is disabled.
Chip Select is enabled.
Reserved.
E8h
7
1
0
0
0
, while the reset state for the three other Chip Select control
R/W
6
1
0
0
0
R/W
Table
5
1
0
0
0
24, enables the Chip Selects, specifies
R/W
4
0
0
0
0
R/W
3
1
0
0
0
Chip Selects and Wait States
Product Specification
R
2
0
0
0
0
eZ80F92/eZ80F93
R
1
0
0
0
0
R
0
0
0
0
0
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