EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 64

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

Table 17. Intel Bus Mode Write States (Separate Address and Data Buses)
PS015313-0508
Table 16. Intel Bus Mode Read States (Separate Address and Data Buses
During Write operations with separate address and data buses, the Intel bus mode employs
four states (T1, T2, T3, and T4) as listed in
Intel bus mode timing is displayed for a Read operation in
Write operation in
driven Low prior to the beginning of State T3, additional wait states (T
until the READY signal is driven High. The Intel bus mode states can be configured for 2
to 15 CPU system clock cycles. In the figures, each Intel bus mode state is 2 CPU system
clock cycles in duration.
assertion of one WAIT state (T
STATE T3
STATE T4
STATE T1
STATE T2
STATE T3
STATE T4
During State T3, no bus signals are altered. If the external READY (WAIT)
pin is driven Low at least one CPU system clock cycle prior to the beginning
of State T3, additional wait states (T
is driven High.
The CPU latches the Read data at the beginning of State T4. The CPU
deasserts the RD signal and completes the Intel
The Write cycle begins in State T1. The CPU drives the address onto the
address bus, the associated Chip Select signal is asserted, and the data is
driven onto the data bus. The CPU drives the ALE signal High at the
beginning of T1. During the middle of T1, the CPU drives ALE Low to
facilitate the latching of the address.
During State T2, the CPU asserts the WR signal. Depending on the
instruction, either the MREQ or IORQ signal is asserted.
During State T3, no bus signals are altered. If the external READY (WAIT)
pin is driven Low at least one CPU system clock cycle prior to the beginning
of State T3, additional WAIT states (T
pin is driven High.
The CPU deasserts the WR signal at the beginning of State T4. The CPU
holds the data and address buses through the end of T4. The bus cycle is
completed at the end of T4.
(Continued)
Figure 13
Figure 12
on page 59. If the READY signal (external WAIT pin) is
WAIT
on page 58 and
) by the selected peripheral.
Table
17.
WAIT
Figure 13
WAIT
) are asserted until the READY pin
) are asserted until the READY
Figure 12
on page 59 also display the
TM
Chip Selects and Wait States
Product Specification
bus mode cycle.
on page 58 and for a
eZ80F92/eZ80F93
WAIT
) are asserted
57