EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 154

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Table 78. I
If 10-bit addressing is being used, then the status code is
a 10-bit address plus the Write bit are successfully transmitted.
After this interrupt is serviced and the second part of the 10-bit address is transmitted, the
I2C_SR register contains one of the codes in
Code
18h
20h
38h
68h
78h
B0h
W = Write bit; that is, the lsb is cleared to 0.
2
I
Addr+W transmitted,
ACK received
Addr+W transmitted,
ACK not received
Arbitration lost
Arbitration lost,
+W received,
ACK transmitted
Arbitration lost,
General call addr
received, ACK
transmitted
Arbitration lost,
SLA+R received,
ACK transmitted
C Master Transmit Status Codes
2
C State
Microcontroller Response Next I
For a 7-bit address: write
byte to DATA, clear IFLG
Or set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP, clear
IFLG
For a 10-bit address: write
extended address byte to
DATA, clear IFLG
Same as code 18h
Clear IFLG
Or set STA, clear IFLG
Clear IFLG, AAK = 0
Or clear IFLG, AAK = 1
Same as code 68h
Write byte to DATA, clear
IFLG, clear AAK = 0
Or write byte to DATA, clear
IFLG, set AAK = 1
Table 79
on page 148.
18h
or
Product Specification
20h
Transmit data byte,
receive ACK
Transmit repeated
START
Transmit STOP
Transmit STOP then
START
Transmit extended
address byte
Same as code 18h
Return to idle
Transmit START when
bus is free
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Same as code 68h
Transmit last byte,
receive ACK
Transmit data byte,
receive ACK
after the first part of
I2C Serial I/O Interface
2
C Action
147