EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 195

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

Table 110. OCI Pins
PS015313-0508
Symbol
TCK
TMS
TDI
TDO
TRIGOUT
OCI Interface
Name
Clock
Test Mode Select
Data In
Data Out
Trigger Output
be accessed via the clock (TCK) and data (TDI) pins. See the Zilog Debug Interface sec-
tion on page 162 for more information about ZDI.
There are five dedicated pins on the eZ80F92 device for the OCI interface.
Four pins—TCK, TMS, TDI, and TDO—are required for IEEE Standard 1149.1-compli-
ant JTAG ports. The TRIGOUT pin provides additional testability features. These five
OCI pins are listed in
Type
Input
Input
Input
(OCI enabled)
I/O
(OCI disabled)
Output
Output
Table 110
.
Description
Asynchronous to the primary CPU system clock. The
TCK period must be at least twice the system clock
period. During RESET, this pin is sampled to select
either OCI or ZDI DEBUG modes. If Low during
RESET, the OCI is enabled. If High during RESET,
the OCI is powered down and ZDI DEBUG mode is
enabled. When ZDI DEBUG mode is active, this pin is
the ZDI clock. On-chip pull-up ensures a default value
of 1 (High).
This serial test mode input controls JTAG mode
selection. On-chip pull-up ensures a default value of
1 (High). The TMS signal is sampled on the rising
edge of the TCK signal.
Serial test data input. On-chip pull-up ensures a
default value of 1 (High). This pin is input-only when
the OCI is enabled. The input data is sampled on the
rising edge of the TCK signal.
When the OCI is disabled, this pin functions as the
ZDA (ZDI Data) I/O pin.
The output data changes on the falling edge of the
TCK signal.
Generates an active High trigger pulse when valid
OCI trigger events occur. Output is tristate when no
data is driven out.
Product Specification
On-Chip Instrumentation
eZ80F92/eZ80F93
188