EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 43
EZ80F92AZ020EG
Manufacturer Part Number
EZ80F92AZ020EG
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020EG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3871
EZ80F92AZ020EG
EZ80F92AZ020EG
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PS015313-0508
HALT Mode
Clock Peripheral Power-Down Registers
Caution:
Execution of the CPU’s HALT instruction places the eZ80F92 device into HALT mode.
In HALT mode, the operating characteristics are:
•
•
•
•
The CPU can be brought out of HALT mode by any of the following operations:
•
•
•
•
•
To minimize current in HALT mode, the system clock should be disabled for all unused
on-chip peripherals via the Clock Peripheral Power-Down Registers.
To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to
be disabled unused on-chip peripherals. Upon RESET, all peripherals are enabled.
The clock to unused peripherals can be disabled by setting the appropriate bit in the Clock
Peripheral Power-Down Registers to 1. When powered down, the peripherals are com-
pletely disabled. To re-enable, the bit in the Clock Peripheral Power-Down Registers must
be cleared to 0.
Many peripherals feature separate enable/disable control bits that must be appropriately
set for operation. These peripheral specific enable/disable bits do not provide the same
level of power reduction as the Clock Peripheral Power-Down Registers. When powered
down, the standard peripheral control registers are not accessible for Read or Write access.
See
Primary crystal oscillator is enabled and continues to operate
The system clock is enabled and continues to operate
The CPU is idle
The Program Counter (PC) stops incrementing
A nonmaskable interrupt (NMI)
A maskable interrupt
A RESET via the external RESET pin driven Low
A Watchdog Timer time-out (if configured to generate either an NMI or RESET upon
time-out)
A RESET via execution of a Debug RESET command
Table 4
During HALT mode, the CPU freezes the last address and drives the address bus
with this value. The GPIO Ports remain as configured by the user. Prior to
entering HALT mode, the data bus is driven Low and the control signals MREQ,
CS3:0, INSTRD, BUSACK, IOREQ, RD, and WR are driven High.
and
Table 5
on pages 37 and 38.
Product Specification
Low-Power Modes
36
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