HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 167

MCU 3V 384K I-TEMP 100-TQFP

HD64F2239TF20I

Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of HD64F2239TF20I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
3.2.2
SYSCR is used to select the interrupt control mode and the detected edge for NMI, select the
MRES input pin enable or disable, and enables or disables on-chip RAM.
Bit
7
6
5
4
3
2
1
0
Bit Name
INTM1
INTM0
NMIEG
MRESE
RAME
System Control Register (SYSCR)
Initial Value R/W
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
The write value should always be 0.
Reserved
This bit is always read as 0 and cannot be modified.
These bits select the control mode of the interrupt
controller. For details of the interrupt control modes,
see section 5.5.1, Interrupt Control Modes and
Interrupt Operation.
00: Interrupt control mode 0 (Interrupt is controlled by
01: Setting prohibited
10: Interrupt control mode 2 (Interrupt is controlled by
11: Setting prohibited
NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
1: An interrupt is requested at the rising edge of NMI
Manual Reset Select
Enables or disables the MRES pin input.
0: The MRES pin input (manual reset) is disabled
1: The MRES pin input (manual reset) is enabled
Reserved
This bit is always read as 0 and cannot be modified.
RAM Enable
Enables or disables the on-chip RAM. The RAME bit
is initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
input
input
The MRES input pin can be used
I bit)
I2 to I0 bits and IPR)
Rev. 6.00 Mar. 18, 2010 Page 105 of 982
Section 3 MCU Operating Modes
REJ09B0054-0600

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