HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 519

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.6
If bits CKS2 to CKS0 in one of TCR_0 and TCR_1 (TCR_2 and TCR_3)* are set to B'100, the 8-
bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be
used (16-bit timer mode) or compare-matches of 8-bit channel 0 (channel 2)* can be counted by
the timer of channel 1 (channel 3)* (compare-match count mode). In the case that channel 0 is
connected to channel 1 in cascade, the timer operates as described below.
Note: * Not available in the H8S/2237 Group and H8S/2227 Group.
12.6.1
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
• Setting of compare-match flags
• Counter clear specification
• Pin output
12.6.2
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare-match A for channel 0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the
settings for each channel.
⎯ The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs.
⎯ The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs.
⎯ If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match,
⎯ The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot
⎯ Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with
⎯ Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with
the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare-
match occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is cleared even if
counter clear by the TMRI01 pin has also been set.
be cleared independently.
the 16-bit compare-match conditions.
the lower 8-bit compare-match conditions.
Operation with Cascaded Connection
16-Bit Count Mode
Compare-Match Count Mode
Rev. 6.00 Mar. 18, 2010 Page 457 of 982
Section 12 8-Bit Timers
REJ09B0054-0600