HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 854

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 24 Power-Down Modes
24.3.2
Sleep mode is exited by any interrupt, or signals at the RES pin, MRES pin, or STBY pin.
• Exiting Sleep Mode by Interrupts
• Exiting Sleep Mode by RES Pin or MRES Pin
• Exiting Sleep Mode by STBY Pin
24.4
24.4.1
A transition is made to software standby mode when the SLEEP instruction is executed while the
SSBY bit in SBYCR = 1 and the LSON bit in LPWRCR = 0, and the PSS bit in TCSR_1
(WDT_1) = 0. In this mode, the CPU, on-chip peripheral modules, and system clock oscillator all
stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip
peripheral modules other than SCI and the A/D converter, and the states of I/O ports are retained.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
24.4.2
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ7 to IRQ0), or by
means of the MRES pin or STBY pin.
• Clearing with an Interrupt
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When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
Setting the RES pin or MRES pin level low selects the reset state. After the stipulated reset
input duration, driving the RES pin or MRES pin high starts the CPU performing reset
exception processing.
When the STBY pin level is driven low, a transition is made to hardware standby mode.
When an NMI, or IRQ7 to IRQ0 interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to
the entire this LSI chip, software standby mode is cleared, and interrupt exception handling is
started.
When clearing software standby mode with an IRQ7 to IRQ0 interrupt, set the corresponding
enable bit/pin function switching bit to 1 and ensure that no interrupt with a higher priority
Software Standby Mode
Transition to Software Standby Mode
Clearing Software Standby Mode
Exiting Sleep Mode