HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 313
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.5.7
In block transfer mode, data transfer is performed with channels A and B used in combination.
Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in
DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in
response to a single transfer request, and this is executed for the number of times specified in
ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either
the transfer source or the transfer destination can be selected as a block area (an area composed of
a number of bytes or words). Table 8.10 summarizes register functions in block transfer mode.
Table 8.10 Register Functions in Block Transfer Mode
Register
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB. Whether a block is to be designated for MARA or for
MARB is specified by the BLKDIR bit in DMACRA.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N
transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,
and N in ETCRB.
Figure 8.14 illustrates operation in block transfer mode when MARB is designated as a block area.
23
23
Block Transfer Mode
15
MARA
MARB
ETCRB
7
7
ETCRAH
ETCRAL
0
0
0
0
0
Function
Source address
register
Destination
address register
Holds block
size
Block size
counter
Block transfer
counter
Initial Setting
Start address of
transfer source
Start address of
transfer destination
Block size
Block size
Number of block
transfers
Rev. 6.00 Mar. 18, 2010 Page 251 of 982
Section 8 DMA Controller (DMAC)
Operation
Incremented/decremented
every transfer, or fixed
Incremented/decremented
every transfer, or fixed
Fixed
Decremented every
transfer; ETCRH value
copied when count reaches
H'00
Decremented every block
transfer; transfer ends
when count reaches
H'0000
REJ09B0054-0600
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