HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 321
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
If a request from another higher-priority channel is generated after burst transfer starts, that
channel has to wait until the burst transfer ends.
If an NMI interrupt is generated while a channel designated for burst transfer is in the transfer
enabled state, the DTME bit in DMABCRL is cleared and the channel is placed in the transfer
disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on
completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is
suspended. If the last transfer cycle of the burst transfer has already been activated inside the
DMAC, execution continues to the end of the transfer even if the DTME bit is cleared.
Full Address Mode (Block Transfer Mode): Figure 8.22 shows a transfer example in which
TEND output is enabled and word-size full address mode transfer (block transfer mode) is
performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
Address bus
TEND
HWR
LWR
Bus release
RD
φ
Figure 8.21 Example of Full Address Mode Transfer (Burst Mode)
DMA
read
DMA
write
DMA
read
Burst transfer
DMA
write
Rev. 6.00 Mar. 18, 2010 Page 259 of 982
DMA
Section 8 DMA Controller (DMAC)
read
Last transfer cycle
DMA
write
DMA
dead
REJ09B0054-0600
Bus release
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