HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 206

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Interrupt Controller
The interrupt source selected is the interrupt with the highest priority level, and whose priority
level set in IPR is higher than the mask level.
Table 5.5
Interrupt Control Mode
0
2
Default Priority Determination: When an interrupt is selected by 8-level control, its priority is
determined and a vector number is generated.
If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.6 shows operations and control signal functions in each interrupt control mode.
Table 5.6
Legend:
O: Interrupt operation control performed.
X:
IM: Used as interrupt mask bit.
PR: Sets priority.
⎯: Not used.
Notes: 1. Set to 1 when interrupt is accepted.
Rev. 6.00 Mar. 18, 2010 Page 144 of 982
REJ09B0054-0600
Interrupt
Control
Mode
0
2
No operation (All interrupts enabled).
2. Keep the initial setting.
INTM1 INTM0
Interrupts Selected in Each Interrupt Control Mode (2)
Operations and Control Signal Functions in Each Interrupt Control Mode
0
1
Setting
0
0
O
X
Selected Interrupts
All interrupts
Highest-priority-level (IPR) interrupt whose priority level is greater
than the mask level (IPR > I2 to I0).
Acceptance
Interrupt
Control
⎯ *
IM
I
1
O
X
8-Level Control
I2 to I0
IM
⎯
⎯ *
IPR
PR
2
Default Priority
Determination
O
O
(Trace)
⎯
T
T