HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 862

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 24 Power-Down Modes
24.10
There are three modes, high-speed, medium-speed, and subactive, in which the CPU executes
programs. When a direct transition is made, there is no interruption of program execution when
shifting between high-speed and subactive modes. Direct transitions are enabled by setting the
LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct
transition interrupt exception processing starts.
24.10.1 Direct Transitions from High-Speed Mode to Subactive Mode
Execute the SLEEP instruction in high-speed mode when the SSBY bit in SBYCR = 1, the LSON
bit in LPWRCR = 1, and the DTON bit = 1, and the PSS bit in TSCR_1 (WDT_1) = 1 to make a
transition to subactive mode.
24.10.2 Direct Transitions from Subactive Mode to High-Speed Mode
Execute the SLEEP instruction in subactive mode when the SSBY bit in SBYCR = 1, the LSON
bit in LPWRCR = 0, and the DTON bit = 1, and the PSS bit in TSCR_1 (WDT_1) = 1 to make a
direct transition to high-speed mode after the time set in STS2 to STS0 bits in SBYCR has
elapsed.
24.11
The PSTOP bit in SCKCR and the DDR of the corresponding port control the φ clock output.
When the PSTOP bit is set to 1, φ clock stops at the end of the bus cycle and the φ clock output is
fixed high. When the PSTOP bit is cleared to 0, the φ clock output is enabled. When the DDR of
the corresponding port is cleared to 0, the φ clock output is disabled and it functions as an input
port. Table 24.4 lists the φ pin states in respective process.
Table 24.4 φ Pin States in Respective Processes
Rev. 6.00 Mar. 18, 2010 Page 800 of 982
REJ09B0054-0600
DDR
PSTOP
Hardware standby mode
Software standby mode, watch
mode, direct transition
Sleep mode, subsleep mode
High-speed mode, medium-
speed mode, subactive mode
φ Clock Output Enable
Direct Transitions
0
⎯
High impedance
High impedance
High impedance
High impedance
1
0
High impedance
Fixed to high
φ output
φ output
1
1
High impedance
Fixed high
Fixed high
Fixed high