HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 624
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 15 Serial Communication Interface (SCI)
Legend:
×: Don’t care
Rev. 6.00 Mar. 18, 2010 Page 562 of 982
REJ09B0054-0600
Bit
3
2
1
0
Bit Name
MPIE
TEIE
CKE1
CKE0
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
Description
Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
Write 0 to this bit in Smart Card interface mode.
When receive data including MPB = 0 is received,
receive data transfer from RSR to RDR, receive
error detection, and setting of the RERF, FER, and
ORER flags in SSR, are not performed.
When receive data including MPB = 1 is received,
the MPB bit in SSR is set to 1, the MPIE bit is
cleared to 0 automatically, and generation of RXI
and ERI interrupts (when the TIE and RIE bits in
SCR are set to 1) and FER and ORER flag setting
are enabled.
Transmit End Interrupt Enable
Write 0 to this bit in Smart Card interface mode.
TEI cancellation can be performed by reading 1
from the TDRE flag in SSR, then clearing it to 0
and clearing the TEND flag to 0, or clearing the
TEIE bit to 0.
Clock Enable 0 and 1
Enables or disables clock output from the SCK pin.
The clock output can be dynamically switched in
GSM mode. For details, refer to section 15.7.8,
Clock Output Control.
When the GM bit in SMR is 0:
00: Output disabled (SCK pin can be used as an
01: Clock output
1×: Reserved
When the GM bit in SMR is 1:
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
I/O port pin)
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