HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 570

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
14.3.10 IEBus Reception Master Address Register 1 (IEMA1)
IEMA1 indicates the lower four bits of the communications destination master unit address in
slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the
contents are changed at the timing of setting the RxS flag in IERSR.
If a broadcast receive error interrupt is selected by the DEE bit in IECTR and the receive buffer is
not in the receive enabled state on control field reception, a receive error interrupt is generated and
the lower 4 bits of the master address are stored in IEMA1. This register cannot be modified.
14.3.11 IEBus Reception Master Address Register 2 (IEMA2)
IEMA2 indicates the upper 8 bits of the communications destination master unit address in
slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the
contents are changed at the timing of setting the RxS flag in IERSR.
If a broadcast receive error interrupt is selected with the DEE bit in IECTR and the receive buffer
is not in the receive enabled state at control field reception, a receive error interrupt is generated
and the upper 8 bits of the master address are stored in IEMA2. This register cannot be modified
by a write.
Rev. 6.00 Mar. 18, 2010 Page 508 of 982
REJ09B0054-0600
Bit
7
6
5
4
3 to 0 ⎯
Bit
7
6
5
4
3
2
1
0
Bit Name
IMA3
IMA2
IMA1
IMA0
Bit Name
IMA11
IMA10
IMA9
IMA8
IMA7
IMA6
IMA5
IMA4
Initial Value
0
0
0
0
All 0
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R/W
R
R
R
R
R
R
R
R
Description
Lower 4 Bits of IEBus Reception Master Address
Indicate the lower 4 bits of the communications
destination master unit address in slave/broadcast
reception.
Reserved
These bits are always read as 0.
Description
Upper 8 Bits of IEBus Reception Master Address
Indicate the upper 8 bits of the communications
destination master unit address in slave/broadcast
reception.