HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 627
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit
3
2
1
0
Bit Name
PER
TEND
MPB
MPBT
Initial
Value
0
1
0
0
R/W
R/(W) *
R
R
R/W
1
Description
Parity Error
Indicates that a parity error occurred during
reception using parity addition in asynchronous
mode, causing abnormal termination.
[Setting condition]
When a parity error is detected during reception
If a parity error occurs, the receive data is
transferred to RDR but the RDRF flag is not set.
Also, subsequent serial reception cannot be
continued while the PER flag is set to 1. In clocked
synchronous mode, serial transmission cannot be
continued, either.
[Clearing condition]
When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains its previous
state when the RE bit in SCR is cleared to 0.
Transmit End
Indicates that transmission has been ended.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
data. When the RE bit in SCR is cleared to 0 its
previous state is retained.
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to
the transmit data.
Section 15 Serial Communication Interface (SCI)
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit
of a 1-byte serial transmit character
When 0 is written to TDRE after reading TDRE
= 1
When the DMAC *
a TXI interrupt request and transfer
transmission data to TDR
Rev. 6.00 Mar. 18, 2010 Page 565 of 982
2
or the DTC *
REJ09B0054-0600
3
is activated by
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