HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 282
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 8 DMA Controller (DMAC)
• DMABCRL
Rev. 6.00 Mar. 18, 2010 Page 220 of 982
REJ09B0054-0600
Bit
7
6
5
4
Bit Name
DTE1B
DTE1A
DTE0B
DTE0A
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Data Transfer Enable 1B
Data Transfer Enable 1A
Data Transfer Enable 0B
Data Transfer Enable 0A
If the DTE bit is cleared to 0 when DTIE = 1, the
DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt
request to the CPU or DTC.
When DTE = 0, data transfer is disabled and
the DMAC ignores the activation source
selected by the DTF3 to DTF0 bits in DMACR.
When DTE = 1, data transfer is enabled and the
DMAC waits for a request by the activation
source selected by the DTF3 to DTF0 bits in
DMACR. When a request is issued by the
activation source, DMA transfer is executed.
0: Data transfer is disabled
1: Data transfer is enabled
[Clearing conditions]
•
•
•
[Setting condition]
When 1 is written to the DTE bit after reading
DTE = 0
When initialization is performed
When the specified number of transfers
have been completed in a transfer mode
other than repeat mode
When 0 is written to the DTE bit to forcibly
suspend the transfer, or for a similar reason
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