HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 706

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 16 I
16.3.6
I
interface.
Bit
7
6
5
4
Rev. 6.00 Mar. 18, 2010 Page 644 of 982
REJ09B0054-0600
2
C bus control register (ICCR) consists of the control bits and interrupt request flags of I
Bit Name
ICE
IEIC
MST
TRS
I
2
C Bus Control Register (ICCR)
2
C Bus Interface (IIC) (Option)
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
Description
I
When this bit is set to 1, the I
enabled to send/receive data and drive the bus since it is
connected to the SCL and SDA pins. ICMR and ICDR can be
accessed.
SCL and SDA output is disabled (and input to SCL and SDA
is enabled) when this bit is cleared to 0. SAR and SARX can
be accessed.
I
When this bit is 1, interrupts are enabled by IRIC.
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they lose in
a bus contention in master mode of the I
slave receive mode, the R/W bit in the first frame immediately
after the start automatically sets these bits in receive mode or
transmit mode by using hardware. The settings can be made
again for the bits that were set/cleared by hardware, by
reading these bits. When the TRS bit is intended to change
during a transfer, the bit will not be switched until the frame
transfer is completed, including acknowledgement.
2
2
C Bus Interface Enable
C Bus Interface Interrupt Enable
2
C bus interface module is
2
C bus format. In
2
C bus