HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 43

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 2.9
Figure 2.10
Figure 2.11
Figure 2.12
Figure 2.13
Figure 2.14
Section 3 MCU Operating Modes
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 3.6
Figure 3.7
Figure 3.8
Figure 3.9
Section 4 Exception Handling
Figure 4.1
Figure 4.2
Figure 4.3
Section 5 Interrupt Controller
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Figure 5.7
Figure 5.8
Figure 5.9
Section 6 PC Break Controller (PBC)
Figure 6.1
Figure 6.2
Section 7 Bus Controller
Figure 7.1
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0. 146
Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2..............148
Block Diagram of Interrupt Controller .................................................................128
Block Diagram of IRQn Interrupts .......................................................................135
Set Timing for IRQnF...........................................................................................136
Block Diagram of Interrupt Control Operation.....................................................143
Interrupt Exception Handling ...............................................................................149
DTC and DMAC Interrupt Control.......................................................................152
Contention between Interrupt Generation and Disabling......................................155
General Register Data Formats (2)......................................................................... 77
Memory Data Formats ........................................................................................... 78
Instruction Formats (Examples) ............................................................................. 90
Branch Address Specification in Memory Indirect Mode...................................... 93
State Transitions..................................................................................................... 97
Flowchart for Access Methods for Registers That Include Write-Only Bits........101
H8S/2258 Memory Map in Each Operating Mode ..............................................109
H8S/2256 Memory Map in Each Operating Mode ..............................................110
H8S/2239 Memory Map in Each Operating Mode ..............................................111
H8S/2238B and H8S/2238R Memory Map in Each Operating Mode .................112
H8S/2236B and H8S/2236R Memory Map in Each Operating Mode .................113
H8S/2237 and H8S/2227 Memory Map in Each Operating Mode.......................114
H8S/2235 and H8S/2225 Memory Map in Each Operating Mode.......................115
H8S/2224 Memory Map in Each Operating Mode ..............................................116
H8S/2233 and H8S/2223 Memory Map in Each Operating Mode.......................117
Reset Sequence (Mode 4).....................................................................................122
Stack Status after Exception Handling (Advanced Mode) ...................................125
Operation When SP Value Is Odd........................................................................126
Block Diagram of PC Break Controller ...............................................................158
Operation in Power-Down Mode Transitions ......................................................162
Block Diagram of Bus Controller ........................................................................166
Rev. 6.00 Mar. 18, 2010 Page xli of lx
REJ09B0054-0600