HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 317

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmit-data-empty and receive-data-full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts.
Figure 8.17 shows an example of the setting procedure for block transfer mode.
and transfer destination
Set number of transfers
Figure 8.17 Example of Block Transfer Mode Setting Procedure
Block transfer mode
Set transfer source
Read DMABCRL
Set DMABCRH
Set DMABCRL
Block transfer
mode setting
Set DMACR
addresses
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Set each bit in DMABCRH.
Set the transfer source address in MARA, and
the transfer destination address in MARB.
Set the block size in both ETCRAH and
ETCRAL. Set the number of transfers in
ETCRB.
Set each bit in DMACRA and DMACRB.
Read DTE = 0 and DTME = 0 in DMABCRL.
Set each bit in DMABCRL.
Set the FAE bit to 1 to select full address
mode.
Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Set the transfer data size with the DTSZ bit.
Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
Set the BLKE bit to 1 to select block transfer
mode.
Specify whether the transfer source or the
transfer destination is a block area with the
BLKDIR bit.
Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
Select the activation source with bits DTF3 to
DTF0.
Specify enabling or disabling of transfer end
interrupts to the CPU with the DTIE bit.
Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Rev. 6.00 Mar. 18, 2010 Page 255 of 982
Section 8 DMA Controller (DMAC)
REJ09B0054-0600