HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 363

MCU 3V 384K I-TEMP 100-TQFP

HD64F2239TF20I

Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of HD64F2239TF20I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
For example, when the DTC vector address table is located in the on-chip ROM, normal mode is
set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for
the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
9.6
9.6.1
The procedure for using the DTC with interrupt activation is as follows:
1.
2.
3.
4.
5.
9.6.2
The procedure for using the DTC with software activation is as follows:
1.
2.
3.
4.
5.
6.
Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM.
Set the start address of the register information in the DTC vector address.
Set the corresponding bit in DTCER to 1.
Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
After one data transfer has been completed, or after the specified number of data transfers
have been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the
DTC is to continue transferring data, set the DTCE bit to 1.
Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM.
Set the start address of the register information in the DTC vector address.
Check that the SWDTE bit is 0.
Write 1 to SWDTE bit and the vector number to DTVECR.
Check the vector number written to DTVECR.
After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not
requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the
SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers
have been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested.
Procedures for Using DTC
Activation by Interrupt
Activation by Software
Rev. 6.00 Mar. 18, 2010 Page 301 of 982
Section 9 Data Transfer Controller (DTC)
REJ09B0054-0600

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