HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 726

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 16 I
16.4.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal.
The slave device compares its own address with the slave address in the first frame following the
establishment of the start condition issued by the master device. If the addresses match, the slave
device operates as the slave device designated by the master device.
Figure 16.14 is a flowchart showing an example of slave receive mode operation.
Rev. 6.00 Mar. 18, 2010 Page 664 of 982
REJ09B0054-0600
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing
Figure 16.13 Example of Master Receive Mode Stop Condition Generation Timing
Slave Receive Operation
Data 2
2
C Bus Interface (IIC) (Option)
Bit 0
8
[6] IRIC clearance
[4] IRTR = 0
[3]
Data 1
A
[8]
1 clock cycle wait time
[4] IRTR = 1
9
[7] ACKB set to 1
[3]
Bit 7
[9] TRS set to 1
1
(MLS = ACKB = 0, WAIT = 1)
Data 2
[10] ICDR read (data 2)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
[11] IRIC clearance
3
4
Data 3
5
6
7
[14] IRIC clearance
8
[15] WAIT cleared to 0
[13] IRTR = 0
[12]
IRIC clearance
A
[13] IRTR = 1
[12]
9
[16] ICDR read (data 3)
Data 3
[17] Stop condition
issued
Stop condition
generated