HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 168
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 168 of 1048
- Download datasheet (6Mb)
Section 3 MCU Operating Modes
3.3
3.3.1
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a
data bus, and part of port F carries bus control signals.
Pins P13 to P11 function as input ports immediately after a reset. Pin 10 and ports A and B
function as address (A20 to A8) outputs immediately after a reset. Address (A23 to A21) output
can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR)
regardless of the corresponding data direction register (DDR) values. Pins for which address
output is disabled among pins P13 to P10 and in ports A and B become port outputs when the
corresponding DDR bits are set to 1.
Port C always has an address (A7 to A0) output function.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-
bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
3.3.2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a
data bus, and part of port F carries bus control signals.
Pins P13 to P11 function as input ports immediately after a reset. Pin 10 and ports A and B
function as address (A20 to A8) outputs immediately after a reset. Address (A23 to A21) output
can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR)
regardless of the corresponding data direction register (DDR) values. Pins for which address
output is disabled among pins P13 to P10 and in ports A and B become port outputs when the
corresponding DDR bits are set to 1.
Port C always has an address (A7 to A0) output function.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16-
bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and
port E becomes a data bus.
Rev. 6.00 Mar. 18, 2010 Page 106 of 982
REJ09B0054-0600
Mode 4
Mode 5
Operating Mode Descriptions
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