HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 549
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Manufacturer:
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(2) Master Address Field
The master address field is a field for transmitting the unit address (master address) to other units.
The master address field is comprised of master address bits and a parity bit.
The master address has 12 bits and are output MSB first.
When more than one unit starts transfer of the broadcast bit having the same value at the same
timing, arbitration is decided by the master address field.
In the master address field, self-output data and data on the bus are compared for every one-bit
transfer. If the self-output master address and data on the bus are different, the unit that loses
arbitration, stops transfer, and enters the receive state.
Since the IEBus is configured with wired AND, a unit having the smallest master address of the
units in arbitration (arbitration master) wins in arbitration.
Finally, only a single unit remains in the transfer state as a master unit after outputting 12-bit
master address.
Next, this master unit outputs a parity bit*, defines the master address to other units, and then
enters the slave address field output state.
Note: * Since even parity is used, when the number of one bits in the master address is odd, the
(3) Slave Address Field
The slave address field is a field to transmit an address (slave address) of a unit (slave unit) to
which a master transmit data. The slave address field is comprised of slave address bits, a parity
bit, and an acknowledge bit.
The slave address has 12 bits and is output MSB first. The parity bit is output after the 12-bit slave
address is transmitted in order to avoid receiving the slave address accidentally. The master unit
then detects the acknowledgement from the slave unit in order to confirm that the slave unit exists
on the bus. When the acknowledgement is detected, the master unit enters the control field output
state. However, the master unit enters the control field output state without detecting the
acknowledgement in broadcast communications.
When more than one unit starts transfer of communications frame at the same timing,
broadcast communications has priority over normal communications, and arbitration occurs.
parity bit is 1.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 487 of 982
REJ09B0054-0600
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