HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 761
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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17.5.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
starts conversion. Figure 17.5 shows the A/D conversion timing. Table 17.3 shows the A/D
conversion time.
As indicated in figure 17.5, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in table 17.3.
In scan mode, the values given in table 17.3 apply to the first conversion time. The values given in
table 17.4 apply to the second and subsequent conversions.
SPL
State of channel 3
State of channel 2
State of channel 0
State of channel 1
). The length of t
Notes:
ADDRA
ADDRB
ADDRC
ADDRD
ADST
ADF
Input Sampling and A/D Conversion Time
(AN3)
(AN2)
1. Vertical arrows indicate instructions executed by software.
2. Data currently being converted is ignored.
(AN0)
(AN1)
Idle
D
varies depending on the timing of the write access to ADCSR. The total
Figure 17.4 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected)
Idle
Idle
A/D conversion 1
Set *
1
A/D conversion 2
Continuous A/D conversion
Idle
A/D conversion result 1
D
) has passed after the ADST bit is set to 1, then
A/D conversion 3
Idle
CONV
Rev. 6.00 Mar. 18, 2010 Page 699 of 982
) includes t
Idle
A/D conversion time
A/D conversion 4
A/D conversion result 2
A/D conversion result 3
D
and the input sampling time
Section 17 A/D Converter
A/D conversion 5 *
A/D conversion result 4
REJ09B0054-0600
2
Clear *
1
Idle
Idle
Idle
Clear *
1
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