HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 723

MCU 3V 384K I-TEMP 100-TQFP

HD64F2239TF20I

Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of HD64F2239TF20I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
The procedure for receiving data sequentially, using the wait states (WAIT bit) for
synchronization with ICDR (ICDRR) read operations, is described below.
The procedure below describes the operation for receiving multiple bytes. Note that some of the
steps are omitted when receiving only 1 byte. Refer to figure 16.11 for details.
Figure 16.11 Flowchart for Master Receive Mode (Receiving 1 Byte) (WAIT = 1)
No
No
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Set ACKB = 0 (ICSR)
Set ACKB = 1 (ICSR)
Set WAIT = 1 (ICMR)
Set WAIT = 0 (ICMR)
Master receive mode
and SCP = 0 (ICCR)
Set TRS = 0 (ICCR)
Set TRS = 1 (ICCR)
Write BBSY = 0
Read ICDR
Read ICDR
IRIC = 1?
IRIC = 1?
End
Yes
Yes
(Example)
[1]
[2]
[3]
[7]
[9]
[11] Clear IRIC flag (cancel wait state).
[12] Wait for end of reception of 1 byte.
[15] Cancel wait mode
[16] Read final receive data.
[17] Generate stop condition.
Set to receive mode
Receive start, dummy read.
Receive wait state (IRIC set at falling edge
of 8th clock cycle)
Set acknowledge data for final receive.
Set TRS to generate stop condition.
(IRIC set at rising edge of 9th clock cycle)
Clear IRIC flag. (IRIC flag should be
cleared when WAIT = 0.)
Section 16 I
Rev. 6.00 Mar. 18, 2010 Page 661 of 982
2
C Bus Interface (IIC) (Option)
REJ09B0054-0600

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