HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 284

MCU 3V 384K I-TEMP 100-TQFP

HD64F2239TF20I

Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of HD64F2239TF20I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 222 of 982
REJ09B0054-0600
Bit
13, 12
11
10
Bit Name
DTA1
Initial Value
All 0
0
0
R/W
R/W
R/W
R/W
Description
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
Data Transfer Acknowledge 1
These bits enable or disable clearing when
DMA transfer is performed for the internal
interrupt source selected by the DTF3 to DTF0
bits in DMACR of channel 1.
It the DTA1 bit is set to 1 when DTE1 = 1, the
internal interrupt source is cleared automatically
by DMA transfer. When DTE1 = 1 and DTA1 =
1, the internal interrupt source does not issue
an interrupt request to the CPU or DTC.
It the DTA1 bit is cleared to 0 when DTE1 = 1,
the internal interrupt source is not cleared when
a transfer is performed, and can issue an
interrupt request to the CPU or DTC in parallel.
In this case, the interrupt source should be
cleared by the CPU or DTC transfer.
When DTE1 = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA1 bit setting.
The state of the DTME1 bit does not affect the
above operations.
0: Clearing is disabled when DMA transfer is
1: Clearing is enabled when DMA transfer is
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
performed for the selected internal interrupt
source
performed for the selected internal interrupt
source

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