HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 746
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 16 I
12. Notes on TRS Bit Setting in Slave Mode
Rev. 6.00 Mar. 18, 2010 Page 684 of 982
REJ09B0054-0600
TRS bit
From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the
rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 16.26)
in the slave mode of the I
effective immediately.
However, at other times (indicated as (b) in figure 16.26) the value set in the TRS bit is put on
hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than
taking effect immediately.
This results in the actual internal value of the TRS bit remaining 1 (transmit mode) and no
acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an
address receive operation following a restart condition input with no stop condition
intervening.
When receiving an address in the slave mode, clear the TRS bit to 0 during the period
indicated as (a) in figure 16.26.
To cancel the holding of the SCL bit low by the wait function in the slave mode, clear the TRS
bit to 0 and then perform a dummy read of the ICDR register.
SDA
SCL
Data transmission
2
C Bus Interface (IIC) (Option)
8
Detection of 9th clock
cycle rising edge
9
Figure 16.26 TRS Bit Setting Timing in Slave Mode
TRS bit set
(a)
ICDR dummy read
Restart condition
2
C bus interface, the value set in the TRS bit in the ICCR register is
1
TRS bit setting hold time
2
Address reception
3
(b)
4
5
6
7
Detection of 9th clock
cycle rising edge
8
A
9
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