HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 631
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Notes: 1. Only 0 can be written to this bit, to clear the flag.
Bit
2
1
0
2. Supported only by the H8S/2239 Group.
3. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0.
Bit Name
TEND
MPB
MPBT
Initial
Value
1
0
0
R/W
R
R
R/W
Description
Transmit End
This bit is set to 1 when no error signal has been
sent back from the receiving end and the next
transmit data is ready to be transferred to TDR.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Multiprocessor Bit
This bit is not used in Smart Card interface mode.
Multiprocessor Bit Transfer
Write 0 to this bit in Smart Card interface mode.
Section 15 Serial Communication Interface (SCI)
When the TE bit in SCR is 0 and the ERS bit is
also 0
When the ERS bit is 0 and the TDRE bit is 1
after the specified interval following
transmission of 1-byte data. The timing of bit
setting differs according to the register setting
as follows:
When GM = 0 and BLK = 0, 12.5 etu after
transmission starts
When GM = 0 and BLK = 1, 11.5 etu after
transmission starts
When GM = 1 and BLK = 0, 11.0 etu after
transmission starts
When GM = 1 and BLK = 1, 11.0 etu after
transmission starts
When 0 is written to TDRE after reading TDRE
= 1
When the DMAC *
a TXI interrupt and transfers transmission data
to TDR
Rev. 6.00 Mar. 18, 2010 Page 569 of 982
2
or the DTC *
REJ09B0054-0600
3
is activated by
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