HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 551

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

(5) Message Length Field
The message length field is a field for specifying the number of transfer bytes. The message length
field is comprised of message length bits, a parity bit, and an acknowledge bit.
The message length has eight bits and is output MSB first. Table 14.3 shows the number of
transfer bytes.
Table 14.3 Contents of Message Length Bits
Note:
This field operation differs depending on the value of bit 3 in the control field: master
transmission (bit 3 in the control bits is 1) or master reception (bit 3 in the control bits is 0).
(a) Master Transmission
(b) Master Reception
Message Length bits (Hexadecimal)
H'01
H'02
.
.
H'FF
H'00
The master unit outputs the message length bits and parity bit. When the parity is correct, the
slave unit returns the acknowledgement and enters the following data field. Note that the slave
unit does not return the acknowledgement in broadcast communications.
In addition, when the parity is not correct, the slave unit decides that the message length field
is not correctly received, does not return the acknowledgement, and returns to the waiting
(monitor) state. In this case, the master unit also returns to the waiting state, and
communications end.
The slave unit outputs the message length bits and parity bit. When the parity is correct, the
master unit returns the acknowledgement.
When the parity is not correct, the master unit decides that the message length bits are not
correctly received, does not return the acknowledgement, and returns to the waiting state. In
this case, the slave unit also returns to the waiting state, and communications end.
* If a number greater than the maximum number of transfer bytes in one frame is
specified, communications are performed in multiple frames depending on the
communications mode. In this case, the message length bits indicate the number of
remaining communications data after the first transfer. In this LSI, after the first transfer,
the message length bits must be specified to the number of remaining communications
data by a program, since these bits are not automatically specified by the hardware.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Number of Transfer Bytes
1 byte
2 bytes
.
.
255 bytes
256 bytes
Rev. 6.00 Mar. 18, 2010 Page 489 of 982
REJ09B0054-0600