HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 600

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
5. Similarly, the above data field load and transmission operations are repeated.
6. The DTC completes the data transfer for the number of specified bytes when data to be
7. A TxRDY interrupt (IETxI) is issued to the CPU when the DTC transfer is completed. In this
8. After the last data transfer has been completed, a transmit normal completion (TxF) interrupt
Notes: 1. As a transmit status interrupt (IETSI), a transmit error termination (TxE) interrupt as
Rev. 6.00 Mar. 18, 2010 Page 538 of 982
REJ09B0054-0600
transfer request by IETxI is generated and the second byte data is written to the transmit
buffer.
transmitted in the last byte is written to. At this time, the DTC does not clear the TxRDY flag.
It, however, clears bit DTCEG5 in the DTC enable register G (DTCERG) not to generate more
DTC transfer request.
interrupt handling routine, the TxRDY flag can be cleared. However, since the TxRDY
interrupt will be generated again after the last byte transfer, the TxRDY flag remains set. (Note
that the LUEE bit should be cleared to 0 because an underrun error occurs to terminate the
transfer if the LUEE bit in IECTR is set to 1.) Note, however, that the TxRDY interrupt should
be disabled because the TxRDY interrupt is always generated.
occurs. In this case, the CPU clears the TxF flag and completes the normal completion
interrupt and clears the SRQ flag to 0.
2. If the control bits sent from the master unit is H'0, H'4, H'5, or H'6 in slave
well as the transmit start detection (TxS) and transmit normal completion (TxF)
interrupts must be enabled. If a transmit error completion interrupt is disabled, no
interrupt is generated even if the transfer is terminated by an error.
transmission, the IEB automatically performs processing and the TxS and TxF flags are
not set.