HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 702
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 16 I
Table 16.2 Transfer Format
SAR
FS
0
0
1
1
16.3.4
ICMR sets the transfer format and transfer rate. It can only be accessed when the ICE bit in ICCR
is 1.
Bit
7
6
5
4
3
Rev. 6.00 Mar. 18, 2010 Page 640 of 982
REJ09B0054-0600
Bit Name
MLS
WAIT
CKS2
CKS1
CKS0
I
2
C Bus Mode Register (ICMR)
2
C Bus Interface (IIC) (Option)
SARX
FSX
0
1
0
1
Initial
Value
0
0
0
0
0
I
SAR and SARX are used as the slave addresses with the I
format.
Only SAR is used as the slave address with the I
Only SARX is used as the slave address with the I
Clock synchronous serial format (SAR and SARX are invalid)
R/W
R/W
R/W
R/W
R/W
R/W
2
C Transfer Format
Description
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
Wait Insertion Bit
This bit is valid only in master mode with the I
When WAIT is set to 1, after the fall of the clock for the final
data bit, the IRIC flag is set to 1 in ICCR, and a wait state
begins (with SCL at the low level). When the IRIC flag is
cleared to 0 in ICCR, the wait ends and the acknowledge
bit is transferred.
If WAIT is cleared to 0, data and acknowledge bits are
transferred consecutively with no wait inserted.
The IRIC flag in ICCR is set to 1 on completion of the
acknowledge bit transfer, regardless of the WAIT setting.
Serial Clock Select 2 to 0
This bit is valid only in master mode.
These bits select the required transfer rate, together with
the IICX 1 and IICX0 bit in SCRX. Refer to table 16.3.
2
C bus format is used.
2
C bus format.
2
C bus format.
2
C bus format.
2
C bus
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