HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 617

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

• Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
1
0
Bit
7
Bit Name
CKS1
CKS0
Bit Name
GM
Initial
Value
0
0
Initial
Value
0
R/W
R/W
R/W
R/W
R/W
Description
Clock Select 0 and 1
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register
setting and the baud rate, see section 15.3.9, Bit
Rate Register (BRR). n is the decimal
representation of the value of n in BRR (see
section 15.3.9, Bit Rate Register (BRR)).
Description
GSM Mode
When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND
setting is advanced by 11.0 etu (Elementary Time
Unit: the time for transfer of 1 bit), and clock output
control mode addition is performed. For details,
refer to section 15.7.8, Clock Output Control.
0: Normal smart card interface mode operation
•
•
1: GSM mode operation in smart card interface
•
•
Section 15 Serial Communication Interface (SCI)
(initial value)
mode
The TEND flag is generated 12.5 etu (11.5 etu
in the block transfer mode) after the beginning
of the start bit.
Clock output on/off control only
The TEND flag is generated 11.0 etu after the
beginning of the start bit.
In addition to clock output on/off control,
high/low fixed control is supported (set using
SCR).
Rev. 6.00 Mar. 18, 2010 Page 555 of 982
REJ09B0054-0600