HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 628

MCU 3V 384K I-TEMP 100-TQFP

HD64F2239TF20I

Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of HD64F2239TF20I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 15 Serial Communication Interface (SCI)
Notes: 1. Only a 0 can be written to this bit, to clear the flag.
• Smart Card Interface Mode (When SMIF in SCMR is 1)
Rev. 6.00 Mar. 18, 2010 Page 566 of 982
REJ09B0054-0600
Bit
7
6
2. Supported only by the H8S/2239 Group.
3.
Bit Name
TDRE
RDRF
DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0.
Initial
Value
1
0
R/W
R/(W) *
R/(W) *
1
1
Description
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
[Clearing conditions]
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
The RDRF flag is not affected and retains their
previous values when the RE bit in SCR is cleared
to 0.
If reception of the next data is completed while the
RDRF flag is still set to 1, an overrun error will
occur and the receive data will be lost.
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and
data can be written to TDR
When 0 is written to TDRE after reading TDRE
= 1
When the DMAC *
a TXI interrupt request and writes data to TDR
When 0 is written to RDRF after reading RDRF
= 1
When the DTC *
interrupt and transferred data from RDR
3
is activated by an RXI
2
or the DTC *
3
is activated by

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