SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 138

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note 1:
Note 2:
Note 3:
Bit
8:7
5:4
3:2
1:0
11
10
9
6
The DPS field has no meaning or effect on memory-to-memory transfers.
To access on-chip peripherals, the transfer size (TrSiz) must be equal to the device port size (DPS).
The CCRn register must be programmed before placing the DMAC in Ready state.
Mnemonic
RelEn
SReq
TrSiz
DAC
SAC
DPS
SIO
DIO
Snoop Request
Bus Release
Request Enable
I/O Source
Source Address
Count
I/O Destination
Destination
Address Count
Transfer Size
Device Port Size
Field Name
Figure 10.4 Channel Control Registers (CCRn) (2/2)
Reset value = 0
Controls whether or not to request bus mastership with snooping. If set, the TX19
core processor’s snoop function becomes valid, allowing the DMAC to use the
processor’s data bus. If cleared, the snoop function is disabled.
1: The snoop function is enabled (i.e., SREQ is used as a bus request signal).
0: The snoop function is disabled (i.e., GREQ is used as a bus request signal).
Reset value = 0
Controls whether or not to respond to the bus release request signal from the TX19
core processor. This bit is valid when the DMAC uses GREQ as a bus request signal.
This bit has no meaning or effect when the DMAC uses SREQ as a bus request
signal because, in that case, the TX19 core processor does not have the capability to
generate a bus release request signal.
1: The DMAC will respond to the bus release request signal from the TX19 core
0: The DMAC will ignore the bus release request signal from the TX19 core
Reset value = 0
Specifies the type of the source device.
1: I/O device
0: Memory
Reset value = 00
Selects the manner in which the source address changes after each cycle.
1x: Fixed (remains unchanged)
01: Decremented
00: Incremented
Reset value = 0
Specifies the type of the destination device.
1: I/O device
0: Memory
Reset value = 00
Selects the manner in which the destination address changes after each cycle.
1x: Fixed (remains unchanged)
01: Decremented
00: Incremented
Reset value = 00
Specifies the amount of data to be transferred in response to a DMA request.
11: 8 bits (1 byte)
10: 16 bits (2 bytes)
0x: 32 bits (4 bytes)
Reset value = 00
Specifies the port size of a source or destination I/O device.
11: 8 bits (1 byte)
10: 16 bits (2 bytes)
0x: 32 bits (4 bytes)
processor, if it has control of the bus. The DMAC will relinquish the bus when the
current DMA bus cycle completes.
processor.
TMP1940CYAF-96
Description
TMP1940CYAF