SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 153

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4.7
Data Packing and Unpacking
DMAC if the programmed transfer size is not equal to the device port size.
wide, four byte-read cycles occur. The four bytes of data are buffered in the DHR before a destination
word-write cycle occurs.
In dual-address mode, the internal 32-bit DHR allows the data to be packed and unpacked by the
For example, if a source I/O peripheral is 8-bits wide and a destination memory device is 32-bits
The following illustrates the byte ordering for packing and unpacking of data.
4n
4n
4n
4n
3
2
1
0
8
I/O Device
D
C
B
A
Figure 10.13 Data Packing and Unpacking
0
TMP1940CYAF-111
Little-Endian
31
D
C
DHR
TMP1940CYAF
B
A
0