SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 341

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DMA Controller (13 of 16)
Mnemonic Name Address
CCR3
Register 3
Channel
Control
DMA
E260H
FFFF
Source
address
count (bits
8 & 7)
00: Incre-
01: Decre-
1x: Fixed
Must be
written as
0.
Normal
completion
interrupt
enable
0: Disabled
1: Enabled
1: Channel
3 start
SAC0
NIEn
mented
mented
15
23
31
Str
W
7
0
0
1
0
Destination
(I/O)
0: Memory
1: I/O
External
request
mode
1: External
0: Internal
Abnormal
termination
interrupt
enable
0: Disabled
1: Enabled
transfer
request
transfer
request
TMP1940CYAF-299
AbIEn
DIO
ExR
14
22
30
6
0
0
1
0
Destination address
count
00: Incremented
01: Decremented
1x: Fixed
Must be
written as
0.
Must be
written as
0.
DAC1
PosE
13
21
29
5
0
0
1
0
Must be
written as
1.
Must be
written as
0.
DAC0
Lev
12
20
28
4
0
0
0
0
R/W
R/W
R/W
Transfer size
0x: 32 bits
10: 16 bits
11: 8 bits
Snoop
request
0: Disabled
1: Enabled
Must be
written as
0.
TrSiz1
SReq
19
27
11
3
0
0
0
0
Bus
release
request
enable
0: Disabled
1: Enabled
Must be
written as
0.
TMP1940CYAF
TrSiz0
RelEn
10
18
26
2
0
0
0
0
Device port size
0x: 32 bits
10: 16 bits
11: 8 bits
Source
(I/O)
0: Memory
1: I/O
Must be
written as
0.
DPS1
SIO
17
Big
25
1
9
0
0
1
0
Source
address
count (bits
8 & 7)
00: Incre-
01: Decre-
1x: Fixed
Must be
written as
0.
Must be
written as
0.
DPS0
SAC1
mented
mented
16
24
W
0
8
0
0
0
0