SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 238

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4.3
13.4.4
Wake-up Feature
Mode 2 (8-Bit UART Mode)
operation, the parity bit can be added to the transmitted character, and the receiver can perform a parity
check on incoming data. Parity can be enabled and disabled through the programming of the PE bit in
the SC0CR. When PE = 1, the SCR0CR.EVEN bit selects even or odd parity.
Mode 3 (9-Bit UART Mode)
parity bit cannot be used; thus, parity should be disabled by clearing the SC0CR.PE bit to 0.
For receive operations, the most-significant bit is stored in the RB8 bit in SC0CR. Reads and writes of
the transmit/receive character must be done with the most-significant bit first, followed by the SC0BUF.
wake up whenever an address character is received. Setting the SC0MOD0.WU bit enables the wake-up
feature. When the SC0CR.RB8 bit has received an address/data flag bit set to 1, the receiver generates
the INTRX0 interrupt.
Example: Transmitting 8-bit UART characters with an odd-parity bit
Setting the SM[1:0] field in the SC0MOD0 to 10 puts the SIO0 in 8-bit UART mode. In this mode of
Setting the SM[1:0] field in the SC0MOD0 to 11 puts the SIO0 in 9-bit UART mode. In this mode, a
For transmit operations, the most-significant bit (9th bit) is stored in the TB8 bit in the SC0MOD0.
In 9-bit UART mode, the receiver wake-up feature allows the slave station in a multidrop system to
Settings in the main routine
P9CR
SC0MOD
SC0CR
BR0CR
IMCCLL
Example of interrupt routine processing
INTCLR
Reg.
if Reg.
Reg.
End of interrupt processing
X = Don’t care,
Clocking conditions:
System clock:
High-speed clock gear: × 1 (fc)
Prescaler clock:
0 then Error
start
– = No change
7
X
0
7
X
SC0CR AND 0x1C
SC0BUF
bit 0
6
0
0
0
6
X
5
1
1
0
1
5
1
1
TMP1940CYAF-196
Goes out first (transfer rate = 9600 bps @fc = 24.576 MHz)
4
X
X
1
1
4
1
High-speed (fc)
fperiph/4 (fperiph = fsys)
3
1
X
0
0
3
0
2
2
0
X
1
1
2
0
3
1
0
0
0
0
0
1
0
0
1
0
1
0
0
0
4
5
Configures P91 (RXD0) to be an input.
Selects 8-bit UART mode and enables the receiver.
Selects odd parity.
Sets the transfer rate to 9600 bps.
Enables the INTRX0 interrupt and sets its priority
level to 4.
Clears the interrupt request.
Checks for errors.
6
parity
odd
TMP1940CYAF
stop