SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 327

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Generator (1 of 2)
Mnemonic Name Address
19.4 Clock Generator (CG)
SYSCR0
SYSCR1
SYSCR2
SYSCR3
ADCCLK
Conversion
Register 0
Register 1
Register 2
Register 3
Register
System
System
System
System
Control
Control
Control
Control
Clock
Clock
Clock
Clock
Clock
ADC
EE00H
EE01H
EE02H
EE03H
EE04H
FFFF
FFFF
FFFF
FFFF
FFFF
High-speed
oscillator
0: Disable
1: Enable
High-speed
oscillator
drive
capability
0: High
1: Low
DRVOSCH
XEN
R/W
7
1
0
SCOUT
output
select
Low-speed
oscillator
0: Disable
1: Enable
Low-speed
oscillator
drive
capability
0: fs
1: fsys
0: High
1: Low
DRVOSCL
SCOSEL
TMP1940CYAF-285
XTEN
R/W
R/W
6
0
0
0
High-speed
oscillator
after exiting
STOP mode
0: Disable
1: Enable
System
clock (fsys)
select
0: High-
1: Low-
Oscillator warm-up time
00: Reserved
01: 2
10: 2
11: 2
speed
(fgear)
WUPT1
SYSCK
speed (fs)
RXEN
R/W
8
14
16
5
1
0
1
/input frequency
/input frequency
/input frequency
ALE output
width select
0: fsys
1: fsys
Low-speed
oscillator
after exiting
STOP mode
0: Disable
1: Enable
fperiph
select
0: fgear
1: fc
ALESEL
WUPT0
RXTEN
FPSEL
R/W
R/W
R/W
4
0
0
0
1
0.5
1.5
R/W
Clock select
after exiting
STOP mode
0: High-
1: Low-
High-speed
oscillator
frequency
divide factor
0: Divide-by-
1: Divide-by-
Standby mode select
00: Reserved
01: STOP mode
10: SLEEP mode
11: IDLE mode
RSYSCK
DFOSC
speed
speed
2
1
STBY1
R/W
3
0
0
1
Oscillator
warm-up
period
(WUP) timer
On writes:
0: Don’t-
1: Start
On reads:
0: Expired
1: Not
TMP1940CYAF
care
WUP
expired
STBY0
WUEF
R/W
2
0
1
PLL lock
0: Locked
1: Unlocked
Prescaler clock select
00: fperiph/4
01: fperiph/2
10: fperiph
11: Reserved
High-speed clock (fc) gear
select
00: fc
01: fc/2
10: fc/4
11: fc/8
ADC conversion clock
(fadc) select
00: fsys/2
01: fsys/4
10: fsys/8
11: Don’t use.
ADCCK1
GEAR1
PRCK1
LUPFG
R/W
1
0
1
0
0
R/W
R/W
1: Pins are
0: Pins are
PLL lock
time select
0: 2
1: 2
ADCCK0
PRCK0
GEAR0
driven in
STOP
mode.
not driven
in STOP
mode.
LUPTM
frequency
frequency
DRVE
16
12
R/W
R/W
/input
/input
0
0
1
0
0
0