SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 54

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.1
5.1.1
5.1.2
Clock Generation
Main System Clock
Subsystem Clock
A crystal can be connected between X1 and X2, or X1 can be externally driven with a clock.
The on-chip PLL can be enabled or disabled (bypassed) during reset by using the PLLOFF pin.
When the PLL is enabled, the input clock frequency is multiplied by four.
The clock gear can be programmed to divide the clock by 2, 4 or 8. (The default is 1/8 on reset.)
Input clock frequency
A 32.768-kHz crystal is connected between XT1 and XT2 (or XT1 can be externally driven with a
clock.)
SLOW mode: The CPU operates off of the low-speed clock.
SLEEP mode: Only the Real-Time Counter (RTC) is operational.
Note 1: The DFOSC bit in the SYSCR1 must be cleared to 0. The default is 0 on reset.
PLL
(For both crystal and external clock)
PLL OFF
Crystal
External clock
TMP1940CYAF-12
ON
Input Frequency Range
16–20 MHz
16–20 MHz
20–32 MHz
5–8 MHz
16 MHz
32 MHz
20 MHz
20 MHz
TMP1940CYAF
fmax
1
1.25 MHz
2.5 MHz
1 MHz
1 MHz
fmin