SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 230

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BR3ADD
(0xFFFF_F284)
BR3CR
(0xFFFF_F283)
Figure 13.19 SIO3 Baud Rate Generator Control Registers (BR3CR and BR3ADD)
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Note 1: The baud rate generator divisor can not be set to 1 in UART mode if the N + (16 – K) / 16 clock
Note 2: To use the N + (16 – K) / 16 clock division function, the value of K must be programmed in the
Note 3: The N + (16 – K) / 16 clock division function can only be used in UART mode. In I/O Interface
BR3ADD. BR3K[3:0]
1111(K
0001(K
0000
division function is enabled. The divisor should be set to 2 or greater in I/O Interface mode.
BR0ADD.BR0K[3:0] field before setting BR0CR.BR0ADDE to 1. However, the N + (16 – K) / 16
clock division function is not usable when BR0CR.BR0S[3:0] = 0000 (N = 16) or 0001 (N = 1).
mode, this must be disabled by clearing BR0CR.BR0ADDE to 0.
thru
Must be
written as
0.
15)
Clock divisor value for baud rate generator
1)
7
7
0
0000 (N
0001 (N
N +
(16–K)/16
function
0: Disabled
1: Enabled
BR3ADDE
BR3CR.BR3ADDE
Invalid
Invalid
6
6
0
or
TMP1940CYAF-188
Clock source for baud rate generator
16)
00
01
10
11
1)
00: T0
01: T2
10: T8
11: T32
BR3CK1
1111 (N
Divided by N
0010 (N
(16 – K) / 16
Internal clock T0
Internal clock T2
Internal clock T8
Internal clock T32
5
5
0
BR3CR. BR3S[3:0]
Invalid
thru
+
1
15)
2)
BR3CK0
4
4
0
0001 (N 1) (Only UART)
1111 (N
0000 (N
Divided by N
BR3CR.BR3ADDE
R/W
thru
Clock divisor value N
Value of K in N+(16–K)/16
BR3S3
BR3K3
15)
16)
3
3
0
0
TMP1940CYAF
BR3S2
BR3K2
0
2
2
0
0
R/W
BR3S1
BR3K1
1
1
0
0
BR3S0
BR3K0
0
0
0
0