SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 60

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EICRCG
(0xFFFF_EE20)
5.2.4
Interrupt Request Clear Register
Name
Read/Write
Reset Value
Function
Example: Enabling the INT0 interrupt
All interrupt sources other than those used for STOP/SLEEP wake-up signaling are controlled by the
INTC block.
Note 1:
Note 2:
IMCGA0.EMCG[01:00] = 10
IMCGA0.INT0EN = 1
IMC0L.EIM[11:10] = 01
IMC0L.IL[12:10] = 101
Clearing the INT0-INT4 and INTRTC interrupt requests, if programmed for STOP/SLEEP wake-
up signaling, requires two register settings: first, the EICRCG register in the CG block, and
then the INTCLR register in the INTC block. The clearing of other interrupt sources is
controlled through the INTCLR register alone.
In cases where INT0-INT4 are not used for STOP/SLEEP wake-up signaling, they are controlled
by the INTC block in the same way as other interrupt sources. INTRTC is controlled by both
the CG and INTC blocks, regardless of whether it is used for wake-up signaling.
7
6
TMP1940CYAF-18
CG block
(Set the INT0 sensitivity to the falling edge)
priority level to 5.)
INTC block
(Set the interrupt sensitivity to the high level, and the interrupt
5
4
3
Clear interrupt request
ICRCG2
000: INT0
001: INT1
010: INT2
011: INT3
TMP1940CYAF
2
ICRCG1
100: INT4
101: Reserved
110: Reserved
111: INTRTC
W
1
ICRCG0
0