SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 64

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.6
bits of the CPU’s Config register need not be altered. It takes a few clock cycles for a gear change to take
effect. Therefore, one or more instructions following the instruction that changed the clock gear value may
be executed using the old clock gear value. If subsequent instructions need be executed with a new clock
gear value, a dummy instruction (one that executes a write cycle) should be inserted after the instruction that
modifies the clock gear value.
prescaler output ( Tn) satisfies the following relationship:
Standby Control Section
setting the Halt bit of the Config register within the TX19 core processor causes the TMP1940CYAF to enter
one of the standby modes — IDLE, SLEEP or STOP — as specified by the SYSCR2.STBY[1:0] bits.
Setting the Doze bit of the Config register causes the TMP1940CYAF to enter IDLE (Doze) mode,
irrespective of the setting of SYSCR2.STBY[1:0].
must be disabled through the Interrupt Controller (INTC).
There is one thing to remember when changing the clock gear value.
The clock gear can be changed by the programming of the GEAR[1:0] bits of the SYSCR1. The RF[1:0]
When the clock gear is used, the prescalars within on-chip peripherals must be programmed so that the
The TMP1940CYAF provides support for several levels of power reduction. While in NORMAL mode,
Prior to a transition to any of the standby modes, all interrupts other than those used for wake-up signaling
The characteristics of the IDLE, SLEEP and STOP modes are as follows:
IDLE:
SLEEP: Only the internal low-speed oscillator and the RTC are operational.
STOP:
The CPU stops.
On-chip peripherals can be selectively enabled and disabled through use of a register bit in a
given peripheral, as shown in Table 5.3.
The whole TMP1940CYAF stops.
Note 1:
Note 2:
Tn < fsys / 2
In Halt mode (i.e., a standby mode entered by setting the Halt bit in the Config register), the
TMP1940CYAF freezes the TX19 core processor, preserving the pipeline state. In Halt mode,
the TMP1940CYAF ignores any external bus requests; so it continues to assume bus
mastership.
In Doze mode (i.e., a standby mode entered by setting the Doze bit in the Config register),
the TMP1940CYAF freezes the TX19 core processor, preserving the pipeline state. In Doze
mode, the TMP1940CYAF recognizes external bus requests.
Peripheral
Table 5.3 IDLE Mode Register Settings
TMRA01
TMRA23
TMRB0
TMRB1
TMRB2
TMRB3
SIO0
SIO1
SIO3
SIO4
WDT
ADC
SBI
TMP1940CYAF-22
IDLE Mode Bit
TA01RUN.I2TA01
TA23RUN.I2TA23
SBI0BR1.I2SBI0
WDMOD.I2WDT
SC0MOD1.I2S0
SC1MOD1.I2S1
SC3MOD1.I2S3
SC4MOD1.I2S4
TB0RUN.I2TB0
TB1RUN.I2TB1
TB2RUN.I2TB2
TB3RUN.I2TB3
ADMOD1.I2AD
TMP1940CYAF