SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 360

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(2) 16-Kbyte on-chip RAM
(3) External memory expansion
(4) 4-channel DMA controller
(5) 4-channel 8-bit timer
(6) 4-channel 16-bit timer
(7) 1-channel real-time counter (RTC)
(8) 4-channel general-purpose serial interface
(9) 1-channel serial bus interface
(10) 8-channel 10-bit A/D converter (with internal sample/hold)
(11) Watchdog timer
(12) 4-channel chip select/wait controller
(13) Interrupt sources
(14) 77-pin input/output ports
(15) Four standby modes
(16) Dual clocks
(17) Clock generator
(18) Little-endian
512-Kbyte on-chip flash
Two channels support both UART and synchronous transfer modes and the other two channels are solely
for UART.
Either I
Conversion time: 10.75 µs @32 MHz
Higher address 31
Lower address
16-Mbyte off-chip address space for code and data
External bus interface with dynamic bus sizing for 8-bit and 16-bit data ports
Interrupt- or software-triggered
4 CPU interrupts:
32 internal interrupts:
11 external interrupts:
IDLE (HALT, DOZE), SLEEP, STOP
Clock for low-power operation: Low-speed clock (32.768 kHz)
RTC clock: Low-speed clock (32.768 kHz)
On-chip PLL (x4)
Clock gear: Divides the operating speed of the CPU by 1/2, 1/4 or 1/8
Byte 0 is the lowest-order byte (bits 7-0).
The address of a word data item is the address of its lowest-order byte (byte 0).
2
C bus mode or clock-synchronous mode can be selected.
11
7
3
24 23
software interrupt instruction
7 priority levels, with the exception of the watchdog timer interrupt
7 priority levels, with the exception of the NMI interrupt
10
6
2
TMP1940FDBF-2
16 15
9
5
1
8 7
8
4
0
0
Word address
TMP1940FDBF
8
4
0