SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 282

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.2 Register Description
16.2.1
16.2.2
The WDT is controlled by two registers called WDMOD and WDCR.
Watchdog Timer Mode Register (WDMOD)
Watchdog Timer Control Register (WDCR)
This register is used to disable the WDT and to clear the WDT binary counter.
Note:
Time-out Period (WDMOD.WDTP[1:0])
WDT Enable (WDMOD.WDTE)
System Reset (WDMOD.RESCR)
Disabling the WDT
disable code (B1H) to the WDCR register.
Enabling the WDT
Clearing the WDT counter
counting process begins again.
WDTP[1:0] field defaults to 00. Figure 16.5 shows possible time-out periods.
the WDTE bit must be followed by a write of a special key code (B1H) to the WDCR register.
This prevents a “lost” program from disabling the WDT operation. The WDT can be re-enabled
only by setting the WDTE bit.
bit is cleared; thus the time-out does not cause a system reset.
The WDT can be disabled by clearing the WDMOD.WDTE to 0 and then writing the special
The WDT can be enabled only by setting the WDTE bit in the WDMOD to 1.
Writing the special clear-count code (4EH) to the WDCR resets the binary counter to zero. The
This 2-bit field determines the duration of the WDT time-out interval. Upon reset, the
Upon reset, the WDTE bit is set to 1, enabling the WDT. To disable the WDT, the clearing of
This bit is used to program the WDT to generate a system reset on a time-out. Upon reset, this
WDMOD
WDCR
WDCR
Writing the disable code (B1H) to the WDCR causes the binary counter to be reset to zero.
0
1 0 1 1 0 0 0 1
0 1 0 0 1 1 1 0
TMP1940CYAF-240
Clears the WDTE bit to 0.
Writes the disable code (B1H) to the WDCR.
Writes the clear-count code (4EH) to the WDCR.
TMP1940CYAF